Search - VHDL DCT IDCT

[Other resource] dct_p

Description: 这是用VHDL语言(硬件描述语言)写的一个二维 8*8块的离散余弦变换(DCT)以及反变换(IDCT).全同步设计,低门数.可以用于多媒体及打印应用领域.-VHDL (hardware description language) wrote a two-dimensional 8 * 8 discrete cosine transform (D CT) and the anti-transform (IDCT). fully synchronous design, low gate count. can be used for multimedia and print applications.
Platform: | Size: 32990 | Author: citybus | Hits:

[Graph program] DCT-vhdl

Description: 这是一个二维 8*8块的离散余弦变换(DCT)以及反变换(IDCT)算法,采用VHDL实现
Platform: | Size: 10711 | Author: liujl | Hits:

[WEB Code] DCT

Description: 一种改进的一维DCT方案设计与实现,采用VHDL硬件语言描述,DCT以及IDCT
Platform: | Size: 313221 | Author: 小金 | Hits:

[Other resource] erweiDCT

Description: 一种改进的一维DCT方案设计与实现,采用VHDL实现,DCT以及IDCT
Platform: | Size: 129792 | Author: 小金 | Hits:

[Algorithm] dct_p

Description: 这是用VHDL语言(硬件描述语言)写的一个二维 8*8块的离散余弦变换(DCT)以及反变换(IDCT).全同步设计,低门数.可以用于多媒体及打印应用领域.-VHDL (hardware description language) wrote a two-dimensional 8* 8 discrete cosine transform (D CT) and the anti-transform (IDCT). fully synchronous design, low gate count. can be used for multimedia and print applications.
Platform: | Size: 32768 | Author: citybus | Hits:

[VHDL-FPGA-Verilog] DCT_vhdl

Description: IDCT-M is a medium speed 1D IDCT core -- it can accept a continous stream of 12-bit input words at a rate of -- 1 bit/ck cycle, operating at 50MHz speed, it can process MP@ML MPEG video -- the core is 100％ synthesizable-IDCT-M is a medium speed 1D IDCT core-- it ca n accept a continuous stream of 12-bit input word 's at a rate of-- 1 bit/ck cycle, operating at 50MHz speed, it can process MP @ ML MPEG video-- the core is 100 % synthesizable
Platform: | Size: 10240 | Author: 陈朋 | Hits:

[Graph program] DCT-vhdl

Description: 这是一个二维 8*8块的离散余弦变换(DCT)以及反变换(IDCT)算法,采用VHDL实现-This is a two-dimensional 8* 8 discrete cosine transform (DCT) and inverse transform (IDCT) algorithms using VHDL realize
Platform: | Size: 10240 | Author: liujl | Hits:

[Documents] DCT

Description: 一种改进的一维DCT方案设计与实现,采用VHDL硬件语言描述,DCT以及IDCT-An improved one-dimensional program design and realization of DCT using VHDL hardware description language, DCT and IDCT
Platform: | Size: 313344 | Author: 小金 | Hits:

[VHDL-FPGA-Verilog] erweiDCT

Description: 一种改进的一维DCT方案设计与实现,采用VHDL实现,DCT以及IDCT-A one-dimensional DCT to improve program design and implementation using VHDL realize, DCT and IDCT
Platform: | Size: 129024 | Author: 小金 | Hits:

[Graph program] dct

Description: this si Arithmetic core,it contains FreeDCT-L and FreeDCT-M.FreeDCT-L is a low power architecture 1-Dimensional 8-point DCT/IDCT core.FreeDCT-M is a moderate speed 1-Dimensional IDCT core
Platform: | Size: 866304 | Author: lilei | Hits:

[VHDL-FPGA-Verilog] dct

Description: 2维DCt源码，可以实现8乘8点数据的2维DCT变换 -2-D DCT-source, you can realize 8 x 8 data 2-D DCT transform
Platform: | Size: 5120 | Author: jz | Hits:

[VHDL-FPGA-Verilog] 8x8IDCT

Description: 8x8 iDCT verilog code 一次輸入八個點-8x8 iDCT verilog code once the importation of eight points
Platform: | Size: 8303616 | Author: Emuil | Hits:

[VHDL-FPGA-Verilog] DCT_IDCT

Description: 离散余弦变换及反离散余弦变换的HDL代码及测试文件。包括VHDL及Verilog版本。可用途JPEG及MEPG压缩算法。-Discrete cosine transform and inverse discrete cosine transform of the HDL code and test files. Including VHDL and Verilog versions. And MEPG can use JPEG compression algorithm.
Platform: | Size: 29696 | Author: caesar | Hits:

[Software Engineering] dct-thesis

Description: Project 2D DCT core - specifications and codes-Project 2D DCT core- specifications and codes
Platform: | Size: 494592 | Author: student | Hits:

[Special Effects] TDC_3

Description: This is a matrixl 8 * 8 discrete cosine transform (DCT) and inverse transform (IDCT) algorithms using VHDL realiz-This is a matrixl 8* 8 discrete cosine transform (DCT) and inverse transform (IDCT) algorithms using VHDL realiz
Platform: | Size: 1024 | Author: helllano | Hits:

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list

[Other resource] dct_p

[Graph program] DCT-vhdl

[WEB Code] DCT

[Other resource] erweiDCT

[Algorithm] dct_p

[VHDL-FPGA-Verilog] DCT_vhdl

[Graph program] DCT-vhdl

[Documents] DCT

[VHDL-FPGA-Verilog] erweiDCT

[Graph program] dct

[VHDL-FPGA-Verilog] dct

[VHDL-FPGA-Verilog] 8x8IDCT

[VHDL-FPGA-Verilog] DCT_IDCT

[Software Engineering] dct-thesis

[Special Effects] TDC_3

[mpeg mp3] mpeg2_idct_hw

[Compress-Decompress algrithms] DCTPROGRAM.ZIP

[VHDL-FPGA-Verilog] attachments_2010_01_29

[VHDL-FPGA-Verilog] DCT_IDCT

[VHDL-FPGA-Verilog] DCT_IDCT

CodeBus www.codebus.net